Recently, as the downsizing of electronic apparatuses and the integration of integrated circuits progress, thermal analysis during the design time becomes a factor indispensable to designing electronic apparatuses. Among the computing methods for thermal analysis is a thermal network method which is widely known. As shown in FIG. 10, the thermal network method divides an analysis target into small areas according to its shape, boundary condition, and the like, and provides nodes for representing the temperatures of the small areas. This makes it possible to obtain solutions of high precision with computational complexity of relatively small scale. In FIG. 10, focusing on a node Ni, the amount of heat occurring from the node Ni is given by:
(the amount of heat flowing out of the node Ni to a node N1)+(the amount of heat flowing out of the node Ni to a node N2)+ . . . +(the amount of heat flowing out of the node Ni to a node Nj).
The thermal network method involves the operation of expressing a target to be analyzed in the form of a thermal equivalent circuit as described above. Initially, the internal of an electronic apparatus is divided into several small areas. Representative points called nodes are provided in these areas. A node is a point for representing the temperature of a certain area, and typically falls on the center of the area. Next, the nodes are coupled to each other with thermal resistances so that the entire electronic apparatus is expressed in the form of a thermal equivalent network. From the thermal network data thus generated, simultaneous linear equations are created which show the energy balance between the individual areas. These equations can be solved to determine the temperatures and heat flow rates of the nodes.
In the area division of the conventional method for generating thermal network data, uniform area division according to the shape of the analysis target is typically performed before nodes are established to generate thermal network data. As employed herein, “uniform area division” refers to dividing the area of a plurality of components coupled into small areas having a size necessary to show the coupling state. For example, Japanese Patent Publication No. 2596847 discloses a method of dividing an analysis target into rectangular small areas and adjusting mismatches between the small areas (see FIG. 11). Moreover, Japanese Patent Laid-Open Publication No. Hei 7-311166 describes a method for area division and thermal resistance generation in which an analysis target is initially divided into rectangular small areas, and thermal resistances are created from nodes to vertices of the rectangular areas as necessary (see FIG. 12).
In recent years, scenes to generate thermal network data on a coupling structure of a large number of components, as typified by a printed circuit board having a large number of components such as a large-scale integrated circuit (LSI) mounted thereon, are on the increase. In such cases, the conventional method for generating thermal network data has the following problems.
A first problem occurs at the time of application of the conventional method for area division. In the conventional method for area division, the uniform area division to a size necessary to show the coupling state is performed on the entire area of a plurality of components coupled, thereby generating small areas. Consequently, when a plurality of components of large and small, various sizes are coupled in an area, the size of the small areas necessary to show the coupling state becomes small. As a result, the number of small areas and the number of nodes increase to make the thermal network data larger in scale. Since the thermal network data, the input data of thermal analysis, is of larger scale, it becomes difficult to apply the thermal analysis during the design time. In other words, it becomes difficult to secure practical calculation speed while ensuring the calculating precision.
For a second problem, the same problem as described above also occurs when the generation of thermal network data takes account of a wiring pattern in addition to the coupling structure of a large number of components. That is, the increase in the scale of the thermal network data makes it difficult to apply the thermal analysis during the design time.